Job Responsibilities
1. Cooperate with front-end engineers to optimize timing, area, power and complete timing analysis;
2. Optimize layout and complete layout verification (RC extraction, ECO, DRC, LVS);
3. Responsible for chip size optimization and IR drop analysis of power;
4. Use Prime Timing to complete static timing analysis, including setup and hold.
Job requirements
1. Major in integrated circuit, computer, electronic engineering, etc.;
2. Well understand EDA tools such as DC, ICC2, Innovus, formality, PT, PTPX;
3. Familiar with languages such as csh, tcsh, Makefile, TCL, perl and python;
4. Familiar with Synopsys/Cadence/Mentor backend tools and processes (ICC2/Innovous/Calibre).